Ram subsystems block level diagram and description for vhdl hack

I am in a project development class and the project we are building is a hack computer using an FPGA device. So the hardware is purchased. One of the items I am tasked with is designing the RAM component and its subsystems. First though, I need to create a block level diagram and description for the random access memory and its subsystem components. Can someone help me with this? I need this quickly also please. If you have any questions or require any additional information please ask asap. Thank you in advance.

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